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Yiwei Chen

FPGA Design & Verification Engineer at ScaleFlux

Yiwei Chen has been an FPGA Design & Verification Engineer at ScaleFlux since 2019. Prior to this, they served as a Research Assistant at Columbia University in the City of New York from 2018.

Yiwei Chen obtained a Bachelor of Engineering - BE in Microelectronics from Xi'an Jiaotong University in 2016. Yiwei then pursued a Master's degree in Electrical Engineering from Columbia University, which they completed in 2018.

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