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Tomasz Bialas is a Senior Digital Design Engineer at Riverlane since April 2022, specializing in the design of Quantum Error Correction decoder hardware cores and performance optimization on modern FinFET processes. Previous experience includes roles at Arm, where Tomasz contributed to Software Test Library development and formal verification as part of CPU engineering, alongside significant internships focused on hardware design and verification. Education includes a Master of Engineering in Electrical and Electronic Engineering from Imperial College London and a Baccalauréat OIB Scientifique from Lycée International de Ferney Voltaire.