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Mathieu Rougnon is a highly skilled Senior Logic Design Engineer at Rambus, specializing in PCIe/CXL prototyping on FPGA since August 2021. Prior experience includes a position as Ingénieur électronique at PLDA, where Mathieu was involved in hardware design from February 2017 to August 2021, and an internship focusing on Verilog design for DMA engines and performance analysis. Additional internships include a role at AXA, working on batch technology in Java, and an operator position at Safran Electrical & Power. Mathieu holds a degree from Grenoble INP - Phelma, having completed studies there from 2014 to 2017, and earlier education at Lycée Laetitia Bonaparte and Lycée Fesch, culminating in a Baccalauréat Scientifique.