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Naresh Patel is a seasoned Principal Physical Design Engineer at onsemi since November 2017, specializing in imaging SOC devices within the Industrial Sensor Group. Prior to this role, Naresh held positions as a Physical Implementation Design Engineer at Intel from September 2008 to November 2017, focusing on complex ASIC devices, and as a Consultant at Sondrel Limited, where expertise was provided in physical and timing closure for ASIC designs across various customer sites in Europe and the USA. Naresh's career also includes significant contributions as a Physical Design Engineer at Xyratex, where work involved the physical layout of an eight million-gate design, and as a Senior Design Engineer at both Fujitsu Microelectronics Europe and GEC Plessey Semiconductors. Naresh holds a B.Sc. in Computer Technology from Teesside University, earned between 1983 and 1988.