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Ritwik Raj is an experienced engineer specializing in design verification and ASIC development. With a background as a Design Verification Engineer at Meta and progressing through roles such as Sr. ASIC Engineer and ASIC Engineer 2 at Juniper Networks, Ritwik has developed a strong expertise in the field. Earlier experience includes an internship at Finisar Corporation. Ritwik holds a Master's of Science degree in Electrical and Electronics Engineering from North Carolina State University and a Bachelor's degree in the same field from Nirma University.