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Laurent Isenegger is an experienced professional in system architecture and performance modeling, currently working at Meta since October 2021, focusing on architecture for the Meta Training and Inference Accelerator and data center modeling. Prior experience includes a senior manager role at Micron Technology, where Laurent led performance analysis for advanced memory and storage subsystems, and a staff engineer position at Qualcomm, specializing in system simulation for Wireless LAN SoCs. Additional roles at Intel Corporation involved modeling solutions for IoT applications and semiconductor performance analysis. Laurent's career also includes positions at CoFluent Design, Temento Systems, and SAGEM, contributing expertise in system-level design, FPGA verification, and embedded software development. Laurent holds a Master's degree in Electronics and Computer Science from CentraleSupélec and a Master's in Signal Processing and Telecommunications from Universidad Politécnica de Madrid.