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Asawari K. is an accomplished Functional Safety Engineer currently at Marvell Technology. With prior experience as a Sr. Technical Communications Manager for Tensilica IP at Cadence Design Systems, Asawari has a strong background in engineering, having worked as a Sr. Design Verification Engineer at PLX Technology and a Hardware Verification Engineer at SUN Microsystems. Asawari began a career as a Design Engineer at Inspira after completing an MSEE degree in ASIC VLSI from San Jose State University between 2002 and 2004. Additionally, Asawari has academic roots from the University of Pune.