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Vivekanand Sistla possesses significant experience in engineering, having worked as a Team Lead at Cyient, where responsibilities included designing Interiors and Electrical systems for German High-Speed Trains from May 2015 to December 2015. Prior to this role, Vivekanand held various positions, including Project Lead, Senior Project Engineer, and Project Engineer at Gowra Engineering Technologies Pvt. Ltd. from August 2006 to December 2014. Education was completed in Mechanical Engineering at Osmania University from 2002 to 2006, with earlier schooling at HCL DAV Public School and Narayana Jr. College.