蹤獲觴豐

Laurent Beaulieu is a seasoned Tech Lead and Senior Hardware Engineer at IRT B-com since February 2015, specializing in FPGA/ASIC design processes and technical architecture for various projects across Europe. Laurent's expertise includes IP design in VHDL, Verilog, and SystemVerilog, alongside FPGA development utilizing Altera and Xilinx technologies. Previous experience encompasses roles as an R&D Engineer at Advanten, where proficiency in FPGA development and digital signal processing was demonstrated, and as a Hardware R&D Engineer at Renesas Mobile Corporation, focusing on RFIC digital design for advanced communication modes. Additional roles include consulting positions and internships in hardware design, showcasing a robust background in embedded systems and digital design methodologies. Laurent holds a Master's degree in Electrical Engineering & Telecom from Polytech'Orl矇ans and a Bachelor's degree from The University of Texas at Dallas.