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Rajesh Kumar is the Senior Fellow, Silicon Engineering Group Director, Circuit and Low Power Technologies at Intel. Rajesh has over 8 years of experience in the semiconductor industry and has worked extensively in the area of circuit design and physical design. Prior to joining Intel, Rajesh worked as a Staff Engineer at Qualcomm where they owned the First Level Instruction Cache custom macro design for two generations of Snapdragon mobile/server processors (10nm Finfet and 14nm Finfet) and a Testchip (16nm Finfet). Rajesh also co-owned the First Level Data Cache custom macro design for the 7nm Server CPU. At AMD, Rajesh was a Senior Design Engineer and worked on a number of Physical Design projects. Rajesh has used industry standard EDA tools like DC, ICC2, Primetime, Innovus etc.

Rajesh Kumar has a Master of Science in Computer Engineering from Texas A&M University and a B.Tech in Electrical Engineering from Indian Institute of Technology, Roorkee.

They work with Gary L. Patton - Corporate Vice President, General Manager, Design Enablement, Matthew J. Adiletta - Senior Fellow Director, Systems Innovation Lab, and Eugene Scuteri - Corporate Vice President, General Manager, Xeon Networking Engineering Group. Rajesh Kumar reports to Ann B. Kelleher, SVP & GM, Technology Development.