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Ramesh Nair serves as the Design Methodology Engineering Manager at Intel Corporation since February 2014, leading the team responsible for sign-off tools, flows, and methodology for CPU core and SoC designs. Previously, Ramesh worked as a Design Automation Engineer, focusing on RC Parasitic Extraction and Timing/Power ECO and STA tools. In addition to their role at Intel, Ramesh has significantly contributed to IEEE in various leadership capacities, including Vice President of Communications & Public Awareness at IEEE-USA, member of multiple committees such as the IEEE MGA Nominations & Appointment Committee, IEEE Ethics and Member Conduct Committee, and Chair of the IEEE Rising Stars Conference in 2019. Ramesh holds a Master's Degree in Computer Engineering from the University of Cincinnati and a Bachelor's Degree in Electronics and Communication Engineering from Amrita Vishwa Vidyapeetham.