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Jay Shah has over five years of experience in the field of Analog Engineering and Teaching. In 2016, they joined efabless.com as an Analog Engineer, where they were responsible for sub-circuit IP development, floor planning during Hydra v2p0 tapeout, and refining custom design flows. Prior to that, they were a Graduate Teaching Assistant at San Jose State University from 2014 to 2016. During their time there, they revolutionized the in-lab experience in analog and RFIC design learning, created lab-manuals, solved student simulation and layout problems, and conducted regular tutorial sessions for undergraduates.

Jay Shah received their Masters in Electrical Engineering from San Jose State University, specializing in analog and RFIC circuits, in 2016.