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Sachin Arkasali is an AMS Verification Engineer currently working at Cyient since January 2023 and at Exiger Technologies since August 2022, specializing in LDO, bandgap reference, level shifter, comparators, clock generator, and ADCs. Prior to these roles, Sachin was an RTL Design Verification Engineer at Maven Silicon from November 2021 to August 2022. Sachin holds a Bachelor of Engineering degree in Electrical, Electronics, and Communications Engineering from KLE Technological University in Hubballi, India, obtained between 2018 and 2021.