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Jay Mistry possesses extensive experience in hardware and software co-design, specializing in the development of RTL for custom IP cores and kernel drivers. Currently, at Cruise since January 2020, Jay focuses on designing and creating RTL for camera data pipelines. Prior experience includes a role at Xilinx as a Senior System and Hardware Design Engineer, where Jay designed low-level hardware components and a C++ functional model for SmartConnect. At Intel Corporation, Jay contributed to high-speed serial I/O implementations and RTL design for server processors, gaining foundational experience as an RTL Design Engineer and a Design Engineer Intern at Texas Instruments. Jay holds a Master of Engineering in Electrical Engineering from UC Berkeley and a Bachelor of Science in Electrical Engineering from the University of Maryland.