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Pavan Devarasetti is an experienced RTL Design Engineer at Cirrus Logic since July 2021, following a tenure as a Graduate Student Researcher at Texas A&M University, where the thesis focused on VLSI architecture optimization for matrix-vector multiplication and power system simulation applications. Pavan has also held positions as an Interim Engineering Intern at Qualcomm, performing design implementation tasks, and as an ASIC Digital Design Engineer at Synopsys Inc, contributing to DDR PHY verification efforts. Earlier experience includes a summer internship at Samsung Electronics, optimizing SRAM memory compiler logic paths. Pavan holds a Master's degree in Computer Engineering from Texas A&M University and a Bachelor's degree in Electronics and Communications Engineering from the National Institute of Technology, Tiruchirappalli. Additionally, Pavan has graded courses related to digital design and circuit theory during the academic career.