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Meena Gupta has extensive work experience in the field of semiconductor design and implementation. Meena started their career at Cadence Design Systems as a Senior Application Engineer, where they worked on various aspects of ASIC design flow and provided support to customers. Meena then joined Cadene Design Systems as a Lead Application Engineer, where they helped customers in tapeout and developed training courses. After that, they worked at Cortina Systems as a Sr. Member of Technical Staff, focusing on ASIC design implementation. Meena also worked at Mentor Graphics as a Place & Route Engineer, and at Cortina Systems again as a Principal Member Technical Staff. Later, they joined Marvell Semiconductor as a Staff Design Engineer, before transitioning to Cavium Inc, where they held various roles including Principal Design Engineer and Sr Lead Engineer. Currently, they are working as a CPU Imp Engineer at Apple. Throughout their career, Meena has gained expertise in floor planning, timing closure, SI fixing, DRC/DRV fixing, and ECO methodologies. Meena has also contributed to the development of automated design flows and written scripts in tcl. Meena's strong technical skills and diverse experience make their a valuable asset in the field of semiconductor design.

Meena Gupta attended Punjab Technical University from 1995 to 1999 and obtained a degree in 1999. The field of study is not specified.