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Neriya Kaplan is a seasoned engineer with extensive experience in verification technologies. Currently serving as a Verification Application Engineer at Cadence Design Systems since September 2015, Neriya has also held roles as Principal Software Engineer and Lead Software Engineer within the Verification Technologies team, focusing on the development of new technologies for verification IPs. Prior experience includes a position as a Verification Engineer at Marvell Semiconductor from March 2013 to September 2015, where Neriya was responsible for the comprehensive verification of CPU subsystems, including test plan definition and UVM environment development. Neriya began a career at Verisense from January 2011 to March 2013, concentrating on test-plans and coverage for LPDDR2 Memory controllers. Neriya holds a B.Sc in Electronic Engineering from Jerusalem College of Technology, obtained in 2011.