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Gitesh G. is a Physical Design Engineer with extensive experience in leading projects related to advanced semiconductor technologies, including 3nm, 5nm, and 7nm processes. Currently employed at Cadence since September 2024 and previously at Synapse Design Inc. and eInfochips (An Arrow Company), Gitesh has specialized in managing block partitioning from netlist to GDSII, supporting the sign-off process, and automating procedures through scripting. Academic credentials include a Master of Technology in Microelectronics and VLSI from the Indian Institute of Technology, Roorkee, and a dual Bachelor of Engineering in Electronics and Telecommunications from the International Institute of Information Technology Pune and Savitribai Phule Pune University. Gitesh's early career included vocational training at Bharat Sanchar Nigam Limited, gaining practical exposure to telecommunications systems.