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Kavish Shah has worked at two companies in the field of hardware verification and ASIC design.

From March 2018 until the present, Kavish has been employed at Arteris IP. Initially starting as a Hardware Verification Intern, Kavish implemented a Regression Infrastructure using NodeJS to coordinate multiple tools for generating RTL and UVM testbenches for highly configurable IP. They also configured daily regressions, utilized RegEx for smart triaging and bucketing fails, and generated reports for regression runs. Kavish created a regression dashboard webpage, displaying regression trend graphs and daily regression summaries using HTML and CSS. Currently, Kavish holds the position of Sr. Hardware Verification Engineer at Arteris IP.

From August 2017 to March 2018, Kavish worked at Scalable Systems Research Labs Inc. as a Jr. ASIC Design Engineer.

Kavish Shah began their education at Sacred Heart High School, although there is no specific start or end year provided for this period. Following this, they attended the University of Mumbai from 2009 to 2011, where they obtained a Higher Secondary School Certificate with a focus on Science. Kavish then pursued a Bachelor of Engineering (B.E.) degree in Electronics and Telecommunication at the same institution from 2011 to 2015. Later, from 2015 to 2017, Kavish attended San Jose State University, where they completed their Master of Science (MS) in Electrical Engineering.