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Anurag Peter is a Wireless Low Power RTL Design Engineer at Apple since February 2021, focusing on power and clock manager RTL design for Wireless System-on-Chip (SoC). Prior to this role, Anurag served as a Senior IP Design Engineer at Intel Corporation from March 2015 to February 2021, where experience included working in a voltage regulator IP/Chiplet team. Anurag's career also includes an internship at Intel Corporation as a SoC Validation Intern in 2014, contributing to power management validation for Intel’s Tablet SoC, and earlier work as a Board Design Engineer at Wipro Technologies, specializing in board debug and redesigns for PBX cards. Anurag earned a Master’s Degree in Electrical and Electronics Engineering from the University of Southern California and a Bachelor’s Degree in Electrical, Electronics, and Communications Engineering from Model Engineering College.