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Tilak Miryala is a distinguished engineer at Ampere, with a career spanning from October 2017 to the present, including roles as Senior Principal Design Engineer and Principal Design Engineer, contributing to the server group. Previously, Tilak served as a Senior Staff Design Engineer at AppliedMicro from December 2015 to October 2017. In 2015, Tilak worked as a Synthesis & STA Consultant at Qualcomm through SmartPlay Technologies and held the position of Lead ASIC Design Engineer at Open-Silicon from June 2008 to August 2015, focusing on synthesis, static timing analysis, constraints for full chip designs, formal verification, and power analysis. Tilak holds an M.Tech in VLSI Design from the Indian Institute of Technology, Kharagpur (2006-2008) and a BE in Electronics and Communication from MVSR Engineering College (2002-2006).