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JIACHENG LIU is a Silicon Design Engineer at Advanced Micro Devices (AMD) since February 2022, specializing in integration level design. In addition, Jiacheng serves as an IC Design - SOC Integration Engineer at Xilinx. Previous experience includes an engineering internship at Gigajot Technology Inc., where Jiacheng developed a Global Gray Counter for digital IC design, and an Electrical Engineer Intern II role at Lam Research, focusing on hardware identification systems for wafer processing machines. Earlier internships at Lam Research involved PCB testing and design, as well as procedures for power distribution and protection for electronic components. Jiacheng holds a Master of Science in Electrical and Computer Engineering and a Bachelor's degree in Electrical and Electronics Engineering from UCLA, along with an Associate degree in Electrical or Computer Pre-Engineering from Green River College.