Kalyan Kakarla is a Staff Engineer at MediaTek and has been handling various projects related to digital design, Verilog, and System Verilog since 2026. Prior to this, Kalyan worked as a Senior Verification Engineer at ACL Digital and SmartSoC Solutions Pvt Ltd from 2022 to 2022 and 2021 to 2022, respectively. Kalyan also gained experience as a Design Verification Engineer at CoQube Semiconductor in 2020 and as an ASIC Verification Engineer at SASIC Technologies Private Limited from 2018 to 2020.
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