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Qiang Lai is an experienced design verification engineer currently at Acacia Communications Inc. since October 2014. Prior experience includes serving as a technical leader at Cisco Systems for over a decade, where Qiang led the ASIC verification team and successfully delivered more than 20 ASICs, utilizing UVM, VMM, and Specman methodologies. Earlier roles involved hardware engineering and ASIC verification at Cisco Systems and Lucent Technologies, with expertise in C/C++ and Verilog testbenches and functional verification at various levels. Qiang holds a Master's degree in Electrical Engineering from Worcester Polytechnic Institute and a Bachelor's degree from Zhejiang University.